Tools in CASTLE’s Design Flow for High-Performance Systems (HPS) – A Brief Description

1.0 Introduction Typically, the design of complex systems depends very much on the application domain. For example, performance is the most critical design parameter for applications like real-time video compression, whereas validation of the design is the most important point in avionics, and automotive electronics is mainly concerned with the final costs of the product. Hence it is unlikely that a single design flow is sufficient to cover all the differing requirements of the various application domains. Therefore CASTLE takes a workbench[1] approach where the user can configure different design flows for the various application domains. For this purpose CASTLE provides a number of tools which can be used in design flows. This paper describes a particular design flow for high-performance applications [8]. The design flow starts with a C/C++ program(s) of the considered application domain. The programs are analyzed to determine the requirements imposed by the application domain. Based on these requirements the designer specifies a suitable processor structure for the particular application domain. The processor structure can be entered on a block diagram level into CASTLE's cosynthesis environment. The cosynthesis generates a synthesizable VHDL description of the processor and a compiler back-end which allows to translate any C/C++ program from the given application domain into the opcode of the designed processor. The main steps of this design flow are performed for designing a programmable video processor which can perform a real-time MPEG-1 decoding [3][5]. A C based implementation of the algorithm, called mpeg_play developed by K. Patel, et al. [6] is used as application program. The reminder of the paper is organized as follows. The next section gives an overview of the different design steps in the HPS design flow. Section 3.0 describes the translation of a C program into a RISC-like sequential assembler code. Section 4.0 presents the tools which are necessary to perform the requirement analysis and to display the analysis results. The tools for performing a first design exploration based on relaxed processor archi-tectures are described in 5.0. Using the results of the requirement analysis and the design space exploration, the designer decides on the most suitable processor structure. Section 6.0 describes how this structure can be entered into CASTLE's cosynthesis environment using the schematic entry. Section 7.0 presents the major steps for the hardware synthesis, and finally, section 8.0 describes the generation of the compiler back-end. Note: This paper contains a preliminary description based …